1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming FinFET semiconductor devices having different fin heights.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Historically, the FET has been a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as so-called short channel effects, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, a FinFET device is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device.
The effective gate width (Weff) of a single FinFET device is determined by the fin height (Fh) and by the number of fins (Nf) on the single FinFET device (Weff=Nf×Fh). Typically, FinFETs are made with a singular constant fin height due to the manner in which they are manufactured. As a result, this typically means that, to achieve different effective widths for two different FinFET devices, the number of fins for each of the devices is different. In designing modern integrated circuit products, device designers may need more flexibility in designing the effective gate width for FinFET devices than is afforded by simply increasing or decreasing the number of fins for such devices. There have been attempts in the past to produce FinFETs with different fin heights. One such technique involved initially forming the fins, then implanting germanium into the fins through a mask layer and then performing an anneal process to form a silicon/germanium region on the fin that may be selectively removed relative to silicon by performing an etching process.
The present disclosure is directed to various methods of forming FinFET semiconductor devices having different fin heights.